Today PCB design is increasingly strict with the layout requirements. The layout basically determines the general orientation of the wiring and the structure, the division of the power and ground planes, and the control of noise and EMI. Therefore, the performance of the PCB design is good or bad. Much depends on whether the layout is reasonable.

Often engineers spend a lot of time and effort on layout, pre-layout—pre-simulation—re-layout—optimization, which accounts for about 50% or more of the entire project design time.

The following summarizes a rough layout procedure and rules for reference .

Many other problems must be considered in the actual circuit design, such as heat dissipation, mechanical properties and the placement of some special circuits. The specific layout criteria are determined according to the actual application.

The layout begins with understanding the schematic diagram of the system. It is necessary to divide the digital, analog, and mixed digital/analog components (see the chip data) in each circuit, and pay attention to the positioning of the power and signal pins of each IC chip.

According to the proportion of each part in the circuit, the wiring area of ​​the digital circuit and the analog circuit on the PCB is preliminarily divided, so that the digital components, analog components and their corresponding wirings are far away from each other and are limited to the respective wiring areas. After the area is divided, the components can be placed. The general sequence is a hybrid device—analog component—digital component—bypass capacitor.

Digital-analog hybrid components must be placed at the junction of the digital signal area and the analog signal area, and pay attention to the correct direction, that is, the digital signal and analog signal pins are directed to the respective wiring areas; pure digital or analog components must be placed Within the respective specified ranges; the crystal oscillator circuit is as close as possible to its driving device.

Noise-sensitive devices should be kept away from high-frequency signal wiring. At the same time, noise-sensitive signals such as reference voltage Uref should be kept away from components that are prone to high noise.

Digital components are generally placed as concentrated as possible to reduce line length and reduce noise. However, if there is signal wiring with timing requirements, it is necessary to adjust the layout according to the line length and structure, which should be determined by simulation. The bypass capacitor needs to be placed as close as possible to the chip power supply pin, especially the high frequency capacitor. A large capacity (such as 47uF) capacitor can be placed near the power interface to keep the power supply stable and reduce low frequency noise interference.